| Section | 1 |
|---|---|
| Instructor(s) | Siegel, Andrew (siegela) |
| Location | Online Only |
| Meeting Times | Monday 5:20pm - 6:50pm |
| Fulfills | Core Systems Elective |
*This course will be conducted remotely and will be online only for Winter 2021*
Textbook: Hennessey and Patterson, "Computer Architecture: A Quantitative Approach", 5th Edition preferred
This course focuses on the design and performance evaluation of modern computer architectures. The emphasis is on microprocessors, chip-multiprocessors and memory hierarchy design, including parallel (multicore) CPUs.
Topics include:
Memory cache designs and optimizations
DRAM technologies
Instruction and data pipelining
Branch prediction for instruction- and data-level paralelism
Dynamic scheduling for instruction- and data-level parallelism
Mulithreading support in hardware and operating system
Data coherency for efficient multithreading
Non-uniform memory access for efficient multithreading
Core Programming
This class is scheduled at a time that conflicts with these other classes: