|Instructor(s)||Siegel, Andrew (siegela)|
|Meeting Times||Monday 5:30pm - 8:30pm|
|Fulfills||Core Systems Elective|
Please note: A syllabus for this course will be available before course registration for this quarter begins.
Textbook: Hennessey and Patterson, "Computer Architecture: A Quantitative Approach", 5th Edition preferred
This course focuses on the design and performance evaluation of modern computer architectures. The emphasis is on microprocessors, chip-multiprocessors and memory hierarchy design, particularly in the context of parallel (multicore) CPUs.
Memory cache designs and optimizations
Instruction and data pipelining
Branch prediction for instruction- and data-level paralelism
Dynamic scheduling for instruction- and data-level parallelism
Mulithreading support in hardware and operating system
Data coherency for efficient multithreading
Non-uniform memory access for efficient multithreading
This class is scheduled at a time that does not conflict with any other classes this quarter.